Power Integrity analysis
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As signal edge rates get faster, designers of today's high-speed digital pc boards encounter problems that were unimaginable a few years ago. Trial and error is time-consuming and expensive, often resulting in over-constrained designs that unnecessarily increase design time and manufacturing costs. Sintecs can analyze and optimize board design to identify potential power integrity problems. Using a trial-and-error approach to optimize the power integrity of a pc board requires multiple design cycles and potentially higher cost compared with simulation of virtual prototypes.
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Power Integrity Factors
Even though designs often require more power to travel across a limited amount of space, several factors still affect the density of a design and how much power it can actually handle. Variables include the amount of space that is actually available (height, width and length), the thickness and number of copper layers in the printed circuit board and how the flow pattern influence the interconnect temperature rise. Understanding each of these elements very early in the design phase is necessary to successfully design power integrity into the system and speed up the design process.
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Today’s low power designs demand high performance ICs using multiple voltage rails, where some are very low. The low voltage design issue of defining the power and ground split-planes to avoid excessive current densities and DC voltage drop can de addressed through power integrity analysis.
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Delivered power
Another issue is the integrity, or absence of noise of the delivered power.
The designer needs to determine the number and location of decoupling capacitors and the goal is to save component cost and board area by avoiding over-conservative (excessive) use of bypass capacitors.
The designer may also want to experiment with the PCB fabrication materials and stack-up to determine the best electrical and cost solution.
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Power Integrity Analysis
Obtaining impedance profiles of the power system network, analysis in the frequency domain (noise at various frequencies and resonant behavior), analysis in the time domain (noise at various points of time) and different isolation studies needs to be performed.
For good decoupling design, studies need to be done on capacitor placement and selection (dielectric types, body sizes and values), via placement, capacitor landing pad design, ferrite bead selection and design and analysis of power islands / power splits.
By using high-speed design, analysis and verification techniques early in the design cycle, designers can eliminate layout iterations and ensure that products are marketed on time.
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